The present invention relates generally to the packaging of integrated circuits. More particularly, improved protective metallurgy is described that works particularly well with copper topped wafers used in bumped chip scale packages.
There are a number of conventional processes for packaging integrated circuits. One approach that is commonly referred to as “flip chip” packaging generally contemplates forming solder bumps (or other suitable contacts) directly on the face of an integrated circuit die. In some situations, the contacts are formed directly on I/O pads formed on the die, whereas in other situations the contacts are redistributed. The die is then typically attached to a substrate such as a printed circuit board or package substrate such that the die contacts directly connect to corresponding contacts on the substrate.
A recent development in integrated circuit design has been to include a relatively thick copper layer on top of the dice at the wafer level. The copper layer can be used for routing and a variety of other purposes. Typically, the copper layer is applied after the wafer fabrication and away from (or at least outside of) the wafer fabrication site. Therefore, the copper layer cannot readily be covered with traditional wafer fabrication dielectric materials such as silicon dioxide or silicon nitride unless the wafer is returned to the fab for further processing, which is an expensive proposition. Therefore, a challenge that has been encountered in using copper topped integrated circuits in bumped and/or flip chip designs relates to how to protect the copper layer without incurring undo costs.